IBM has introduced an innovative prototype chip featuring approximately a billion transistors within an area no larger than a fingernail. This new design boasts a transistor density that is double that of the company’s previous leading technology announced last year. This advancement could potentially drive faster and more energy-efficient computing solutions for the coming decade. For over fifty years, chip manufacturers have enhanced computing power by adhering to Moore’s Law, which emphasizes the importance of increasing transistor density on chips. However, as transistors reach sizes close to the quantum mechanical limits, traditional methods of scaling down have become increasingly challenging.
To overcome these limitations, IBM’s latest chip employs a strategy reminiscent of urban development: vertical stacking. Dubbed ‘nanostacking,’ this architecture stacks transistors in two layers on a silicon substrate, representing a significant leap in chip design. Jay Gambetta, the director of IBM Research, underscored the transformative nature of this approach during a recent press conference, projecting widespread adoption of nanostacked chips in data centers over the next decade due to their enhanced energy efficiency. Compared to IBM’s prior designs, the new architecture can perform up to 40% more tasks in the same timeframe while consuming less energy. This technology offers a versatile framework for transistor arrangement, with plans for collaboration with semiconductor manufacturers to bring these chips to market.
The construction of IBM’s chip resembles a multi-layered cake, where transistors are fabricated on one silicon layer, followed by an additional layer of silicon, upon which a second set of transistors is built. This dual-layer structure employs complementary field-effect transistors (CFETs), allowing improved performance through staggered alignment that facilitates efficient wiring. This contrasts with other methods employed by companies like AMD and Huawei, which use independent fabrication techniques for each layer. While IBM is not alone in exploring CFET technology, its unique approach to layer alignment is anticipated to enhance performance significantly. As the industry prepares for production, challenges such as maintaining low manufacturing temperatures and managing potential errors in layer alignment remain critical. However, IBM’s success in achieving these objectives could mark a pivotal moment in semiconductor technology and its evolution.
Source: IBM has unveiled chip technology that could help extend Moore’s Law another decade via MIT Technology Review